1. Field of Disclosure
The present disclosure relates to apparatus and methods for non-volatile data storage.
2. Description of Related Technology
In three-dimensionally selectable memory arrays, it is desirable to minimize line resistances of lines that carry addressing signals and to maximize utilization of such lines, for example by sharing of resources in multiple directions.
One example of a three-dimensionally addressable array of non-volatile memory cells (a.k.a. non-volatile storage elements or “NVSE's”) uses variable resistance memory elements. Each may be set to either a low or high resistance states and it (the variable resistance memory element) remains in that set state until subsequently re-set to the initial condition. The variable resistance memory elements are each connected between two orthogonally extending conductors (typically vertically extending, bit lines and horizontally extending word lines) where they cross each other in a three-dimensional array organized as stacked layers. The state of each such memory element is typically changed by proper voltages being placed on the intersecting conductors (on the bit lines and on the word lines). Since these voltages inherently spread along their respective bit lines and word lines so as to also be applied to a large number of other unselected memory elements (because they are connected along the same conductors as the selected memory elements being programmed or read), diodes are commonly connected in series with the variable resistive elements in order to reduce leakage currents that can flow through them. The desire to perform data reading and programming operations with a large number of memory elements in parallel results in reading or programming voltages being applied to a very large number of other memory elements. An example of an array of variable resistive elements and associated diodes is given in U.S. Patent Application Publication No. US 2009/0001344.